IBM and Samsung have announced a breakthrough in semiconductor design that has the potential to reduce energy usage by 85%.
The new vertical transistor breakthrough could help the semiconductor industry continue its continuing journey to deliver significant improvements, including:
- Potential device architecture that enables semiconductor device scaling to continue beyond nanosheet.
- smartphone batteries that could go over a week without being charged, instead of days.
- Energy intensive processes, such as cryptomining operations and data encryption, could require significantly less energy and have a smaller carbon footprint.
- Continued expansion of Internet of Things (IoT) and edge devices with lower energy needs, allowing them to operate in more diverse environments like ocean buoys, autonomous vehicles, and spacecraft.
"Today's technology announcement is about challenging convention and rethinking how we continue to advance society and deliver new innovations that improve life, business and reduce our environmental impact," Dr. Mukesh Khare, VP, Hybrid Cloud and Systems, IBM Research. "Given the constraints the industry is currently facing along multiple fronts, IBM and Samsung are demonstrating our commitment to joint innovation in semiconductor design and a shared pursuit of what we call 'hard tech.'"
Moore's Law, the principle that the number of transistors incorporated in a densely populated IC chip will approximately double every two years, is quickly nearing what are considered insurmountable barriers. Simply put, as more and more transistors are crammed into a finite area, engineers are running out of space.
Historically, transistors have been built to lie flat upon the surface of a semiconductor, with the electric current flowing laterally, or side-to-side, through them. With new Vertical Transport Field Effect Transistors, or VTFET, IBM and Samsung have successfully implemented transistors that are built perpendicular to the surface of the chip with a vertical, or up-and-down, current flow.
The VTFET process addresses many barriers to performance and limitations to extend Moore's Law as chip designers attempt to pack more transistors into a fixed space. It also influences the contact points for the transistors, allowing for greater current flow with less wasted energy. Overall, the new design aims to deliver a two times improvement in performance or an 85% reduction in energy use as compared to scaled finFET alternatives.